The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A memory device includes a memory device controller and one or more memory integrated circuit chips in communication with the memory device controller. The memory device controller sends commands to the memory integrated circuit chips for execution. For example, the memory device controller may send write commands to store data in the memory integrated circuit chips. One type of memory device is binary and Multi-Level Cell (MLC) NAND flash memory capable of high data storage densities and high performance. In NAND flash, a “page” or group of bits at a time is written to the non-volatile memory.
However, a power failure (such as due to hot removal, brownout, blackout or the like) may cause data corruption or loss when writing data to memory. In flash memory, if a power failure occurs during a write cycle/program operation, something less than all of the bits of the page may be programmed successfully in the non-volatile memory. When the page containing unsuccessfully programmed bits is read back, some bits may have the new value, some will have the old value and, as a result, the page may be corrupted.